Back in February, Cadence laid our their vision of the path to a fully autonomous chip design agent
Cadence
AI silicon complexity is outpacing engineering scale—even at NVIDIA’s headcount. Autonomy is becoming existential, not a nice-to-have. And EDA vendors are rusing in to fill that need.
In February, Cadence Design rocked the chip world by announcing they had developed the world’s first agentic AI that can automate the tasks that comprise the art of turning chip specifications into a verified design. As I noted then, this new “Super Agent” can significantly speed the time needed and deliver some 10X productivity improvements for coding designs and test benches. The Super Agent, born from Cadence’s acquisition of ChipStack last year, creates test plans, orchestrates regression testing, debugs issues, and automatically fixes them, based on a “mental model” of the design and accesses other agentic AI to complete the steps. (We note with pride that both Cadence and Nvidia are clients of Cambrian-AI Research.)
The ChipStack AI Super Agent ties all the design pieces together to work autonomously to orchestrate the end to end design process, eventually tying all the elements together using the Cadence EDA suite.
Cadence
Didn’t Cadence Already Do This?
Cadence had taken the first step, but the process still relied on step-by-step prompts to orchestrate the workflow. A human still had to step through the process, iterating and converging on a design that meets specs at an desired set of parameters and tradeoffs.
That is a great step forward, but a demanding customer, a.k.a. Nvidia, needed more. Nvidia wanted a fully automated process for developing and validating Register-Transfer Level (RTL), a design abstraction which models a synchronous digital circuit in terms of the flow of digital signals (data) between hardware registers, and the logical operations performed on those signals. Cadence accepted the challenge; Nvidia needed to see dramatic breakthroughs in design cycles to meet their aggressive business goals. And Nvidia brought a lot of GPUs, Nemotron3 and the new OpenShell sandbox, a secure agentic implementation of OpenClaw.
Now, the Level 5 ChipStack AI Super Agent evaluates intermediate results, determines next actions and iterates toward closure across tasks such as specification understanding, RTL generation, verification planning, formal analysis, simulation, debug and design convergence.
The Cadence and Nvidia collaboration resulted in a ChipStack AI Super Agent that operates at Level-5 autonomy, independently executing complex chip design and verification workflows while allowing engineers to inspect, guide and collaborate as needed.
Working within the Nvidia Open Shell sandbox, the Cadence Super Agent now works through the Design and Verification Workflow with little-to-no human involvement.
Cadence
What did Nvidia Say?
On stage at the Computex Keynote, Nvidia CEO Jensen Huang was visibly proud of the combined Cadence/Nvidia team for what they had accomplished: an agent, which took in the design team’s requirements and produced a validated circuit. In fact, the new super-super-agent (my silly name, not Cadence’s), which orchestrated the equivalent of thousands of engineers and millions of verification tests, was able to complete the verification loop in less than a day. Thats a 40X improvement over the just recently announced 10X improvement announced in February!
Here’s the video Jensen shared:
A key Cadence differentiator is that autonomous agent behavior is tightly coupled with the company’s core physics-based design and verification engines. This keeps AI-directed actions grounded in proven computational models and signoff-accurate results, creating the trust needed for bet-your-company engineering programs.
Nvidia was able to achieve a 40-fold reduction in verification using the new level 5 Super Agent.
Cadence
Now What?
This work is an engineering collaboration between Cadence R&D and NVIDIA’s product teams. The productization of this technology is in flight and is expected to be announced in the second half of 2026.
The path forward is clear: Cadence will apply this Super Agent methodology to more of the EDA design tools and processes. Will this eliminate electronic design jobs? Hardly. They will move up the stack, allowing senior design engineers to focus on what they do best, and greatly reduce the part of the job they hate the most: boring babysitting of various design tools as they churn away for hours. And the younger set of engineers can learn much faster, honing their skills to replace the senior design engineers when they head off to Maui for a well deserved retirement.
Disclosures: This article expresses the opinions of the author and is not to be taken as advice to purchase from or invest in the companies mentioned. My firm, Cambrian-AI Research, is fortunate to have had many semiconductor firms as our clients, including Baya Systems BrainChip, Cadence, Cerebras Systems, D-Matrix, Esperanto, Flex, Groq, IBM, Intel, Micron, NVIDIA, Qualcomm, Graphcore, SImA.ai, Synopsys, Tenstorrent, Ventana Microsystems, and scores of investors. I have no investment positions in any of the companies mentioned in this article. For more information, please visit our website at https://cambrian-AI.com.
